The field of the present invention relates to interface control devices and methods for control processors and digital signal processors and more particularly to digital simultaneous voice and data (DSVD) and statistical multiplexing (stat mux) systems and methods including control processors and digital signal processors.
Art related to the present invention includes systems and methods for processing multiple channels of data provided in opposite directions in order to support digital simultaneous voice and data (DSVD) communication between a control processor (CP) and a digital signal processor (DSP) connected to plural selected peripherals including, for example, a public switch telephone (PSTN) line, a phone or microphone, or a video connection.
Such multiple channels have in the past transmitted command packets, data packets of various types, debug messages, and bulk delay signals through a random access memory (RAM) interface. It is known for each channel in such systems to have a fixed RAM region with associated interrupt overhead. This limits data throughput and causes excessive interrupts.
It is accordingly intended to accomplish a high communication rate in DSVD systems without excessive interrupts.
According to the present invention, a digital simultaneous voice and data (DSVD) system includes a communications random access memory (COMMRAM) including at least one dynamically reconfigurable COMMRAM channel memory region for concurrently channeled bidirectional data traffic and a digital signal processor (DSP) including a plurality of FIFO elements for storing information to be communicated with selected external peripheral systems.